library IEEE;
use IEEE.std_logic_1164.all;

entity RxUnit is
  port (
    clk, reset : in std_logic;
    enable : in std_logic;
    rd : in std_logic;
    rxd : out std_logic;
    data : in std_logic_vector(7 downto 0);
    FErr, OErr, DRdy : out std_logic);
end RxUnit;
